Real-Time Verification of Statemate Designs

Real-Time Veri cation of Statemate Designs

This paper presents an approach towards real-time veriication of Statemate 1 designs. Statemate is a widely used design tool for embedded control units. These embedded control units are usually contained in industrial products and often implement concurrent systems. In our approach designs including all timing information are translated into untimed Kripke Structures which are optimized and the...

An Axiomatic Theory of StateCharts

Executive Summary Statecharts provide for the detailed graphical description of real-time computing systems. Extended Real Time Logic (ERTL) provides for the axiomatic description of real-time computing systems. The StateMate tool provides powerful facilities for the construction and validation of Statecharts, using a conceptually simple graphical user interface. In this paper we develop a mapp...

Verification of a Radio-Based Signaling System Using the STATEMATE Verification Environment

With the trend to partially move safety-related features from courtyards into on-board control software, new challenges arise in supporting such designs by formal verification capabilities, essentially entailing the need for a model-based design process. This paper reports on the usage of the STATEMATE Verification Environment to model and verify a radio-based signaling system, a trial case stu...

Transformation of the Ravenscar Profile Based Ada Real-time Application to the Verification-ready Statecharts: Reverse Engineering and Statemate approach

The Ravenscar Profile is a subset of Ada95 tasking model which removes the Ada’s unsafe real-time characteristics and allows high-integrity of system. By the Ravenscar Profile, Ada95 can meet the determinism on system behavior. It also allows schedulability analysis and formal verification on the concurrent model of system. But the formal verification may be additional hard works to improve val...

A Compositional Real-Time Semantics of STATEMATE Designs